The present invention relates to the field of integrated circuits, and, more particularly, to integrated circuit devices having capacitors.
Capacitors are used in semiconductor devices such as integrated circuits (ICs) for storing electrical charge. In ICs such as a dynamic random access memory (DRAM), capacitors are used for storage in the memory cells. Typically, capacitors formed in ICs include a lower electrode made of, e.g., polycrystalline silicon (polysilicon), a dielectric layer made of, e.g., tantalum pentoxide and/or barium strontium titantate, and an upper electrode made of, e.g., titanium nitride, titanium, tungsten, platinum or polysilicon.
In recent years, the development of the semiconductor memory device has required higher packing density, and the area occupied by a capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor because of its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell. Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance. This can be accomplished with a metal electrode capacitor, for example, which also may include a high-k dielectric.
Traditionally, interconnection between two conductors in a semiconductor device has been provided by a plug structure such as a tungsten plug, for example, for an electrical connection between first and second metal lines. Such structures require three separate processing steps including one for the formation of each of the two conductors and one for the formation of the tungsten plug structure.
Additionally, greater interest has been shown by manufacturers of semiconductor devices in the use of copper and copper alloys for metallization patterns, such as in conductive vias and interconnects. Copper, compared to aluminum, has both good electromigration resistance and a relatively low electrical resistivity of about 1.7 xcexcohm cm. Unfortunately, copper is difficult to etch. Consequently, dual damascene processes have been developed to simplify the process steps and eliminate a metal etch step to form copper interconnects. Dual damascene processes are also used with aluminum interconnects.
A dual damascene structure has a bottom portion or via that contacts an underlying conductor and replaces the function of a plug structure in a traditional interconnect structure. The dual damascene structure also has a top portion or inlaid trench that is used for the formation of a second conductor. Because the bottom and top portions of a dual damascene structure are in contact with each other, they can be filled simultaneously with the same conductive material, e.g. copper. This eliminates the need to form a plug structure and an overlying conductive layer in separate processing steps.
In the dual damascene process, capacitors are usually formed in a separate level by depositing a first conductive layer, forming the dielectric therebetween, forming a second conductive layer, and then patterning and etching the layered structure. The conductive layers are typically formed of poly-silicon or titanium nitride, for example. Next an oxide is formed over the capacitors and results in surface topographies above the capacitors. This requires chemical mechanical polishing (CMP) to planarize the oxide layer before subsequent layers are formed.
Thus, the conventional process of making capacitors requires additional time due to the etching of the conductive layers as well as the CMP step. Also, if forming a capacitor with metal electrodes, i.e. a metal-insulator-metal (MIM) capacitor, the metal etch step required is not fully compatible with the dual damascene process. In other words, as discussed above, the dual damascene process is used specifically to avoid metal etching; therefore, using a metal etch step within a dual damascene process is undesirable.
As can be seen from the above discussion, there is a need for integration of a high-density metal electrode capacitor which is compatible with the dual damascene process.
In view of the foregoing background, it is therefore an object of the invention to provide a method of making an integrated circuit device with the dual damascene process and including a high-density capacitor having metal electrodes.
It is another object of the invention to provide an integrated circuit device including a high-density capacitor having metal electrodes and which is compatible with dual damascene interconnect structures.
These and other objects, features and advantages in accordance with the present invention are provided by a method of making an integrated circuit device including an interconnect structure and a capacitor, the interconnect structure comprising a metal line and a contact, and the capacitor comprising upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The first conductive layer may be formed by electroplating copper while masking the second opening, and may also include a barrier metal layer to at least line the first opening. The barrier metal layer preferably comprises tantalum nitride.
Also, the step of simultaneously forming the first opening and the second opening may comprise: simultaneously forming an upper portion of the first opening and an upper portion of the second opening; and simultaneously forming a lower portion of the first opening and a lower portion of the second opening. Additionally, the upper portion of the first opening may have a greater width than the lower portion of the first opening, and the upper portion of the second opening may have substantially a same width as the lower portion of the second opening.
The dielectric layer may be formed of a lower dielectric layer portion, an etch stop layer and an upper dielectric layer portion. Thus, the upper portion of the first opening and the upper portion of the second opening may be formed simultaneously in the upper dielectric layer portion and the etch stop layer. Also, the lower portion of the first opening and the lower portion of the second opening may be formed simultaneously in the lower dielectric layer portion.
The capacitor may be formed by depositing a lower metal layer to at least line the second opening and to form the lower metal electrode, forming the capacitor dielectric layer on the lower metal layer, depositing an upper metal layer on the capacitor dielectric layer to form the upper metal electrode. Also, a second conductive layer may be selectively deposited to fill a remaining portion of the second opening. This second conductive layer preferably comprises copper, and the upper and lower metal electrodes of the capacitor preferably comprise tantalum nitride. The capacitor dielectric may be a high-k dielectric having, e.g., a dielectric constant greater than about 25.
The advantages in accordance with the present invention are also provided by an integrated circuit device including a dielectric layer adjacent a semiconductor substrate having first and second openings therein, an interconnect structure in the first opening and comprising a metal line and a metal contact depending therefrom, and a capacitor in the second opening and comprising upper and lower metal electrodes with a capacitor dielectric layer therebetween. The capacitor may have a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Also, the edges of the lower electrode and the capacitor dielectric layer may terminate at the upper surface of the capacitor.
Again, with respect to the method as set forth above, the dielectric layer may comprise a lower dielectric layer portion, an etch stop layer, and an upper dielectric layer portion. Thus, the metal line of the interconnect structure is preferably in the upper dielectric layer portion and the etch stop layer of the dielectric layer, and the contact of the interconnect structure is preferably in the lower dielectric layer portion of the dielectric layer. Also, the capacitor is preferably in the upper dielectric layer portion, the etch stop layer, and the lower dielectric layer portion of the dielectric layer.